Accompanied with continuous advancement of semiconductor manufacturing techniques, the element size in integrated circuits is constantly scaled down, and metal-oxide-semiconductor (MOS) transistor gradually becomes the primary element for the design of integrated circuits. However, MOS transistor has a structure more vulnerable to ESD induced failure than that of bipolar junction transistor (BJT). When a surge on the input voltage of an integrated circuit is applied to the internal circuit via a pad, it is possible to damage the MOS transistors in the internal circuit, and it is therefore an important issue for the design of an integrated circuit with an ESD protection circuit between the pad and internal circuit by which a release path for ESD current is built-up during an ESD event so as to protect the internal circuit from damage.
FIG. 1a shows a typical layout 1 of an ESD protection device, which includes a fingers structure to provide the ESD protection function. Unfortunately, the fingers of the ESD protection device in an integrated circuit are hardly to be turned on uniformly during an ESD event due to their inherent structure difference resulted from the fingers arrangement, resulting in that the ESD current will concentrates in a small region of the fingers structure and thus burns out the ESD protection device. To solve the difficulty, it has been proposed two improved ESD protection circuits 10 and 30, as shown in FIGS. 1b and 1c, respectively.
In FIG. 1b, an ESD protection circuit 10 to enhance an ESD protection device 12 connected between an input pad 24 and ground GND to be turned on uniformly during an ESD event comprises, between the input pad 24 and ground GND, an NMOS transistor 14 connected in series with a substrate resistor 16 resulted from the substrate that the integrated circuit is formed thereon, and a capacitor 18 and a resistor 20 connected in series with the node 22 therebetween connected to the control gate of the NMOS transistor 14. Once upon an ESD event, the triggering circuit composed of the capacitor 18 and resistor 20 generates a triggering signal to turn on the NMOS transistor 14, and the substrate potential is further pumped to a higher level by the substrate resistor 16, thereby enhancing the fingers of the ESD protection device 12 to be turned on uniformly.
Another ESD protection circuit 30, in FIG. 1c, for an ESD protection device 32 connected between an input pad 31 and ground GND to be turned on uniformly during an ESD event, comprises a PNP transistor 34 and a substrate resistor 36 connected between the input pad 31 and ground GND with the base of the PNP transistor 34 connected with a supply voltage VCC, and a capacitor 37 connected between the supply voltage VCC and ground GND. When an ESD event is occurred, the capacitor 37 control the timing of turning on the PNP transistor 34, and the substrate potential is further pumped to a higher level by the substrate resistor 16, thereby enhancing the fingers of the ESD protection device 32 to be turned on uniformly.
The ESD protection circuits 10 and 30 shown in FIGS. 1b and 1c both employ an RC circuit composed of passive devices to control the pumping of the substrate potential during an ESD event for the trigger voltages of the ESD protection devices 12 and 32 to be lowered. An example of such type of circuit is referred to the MOS structure with improved substrate-triggered effect for on-chip ESD protection disclosed by U.S. Pat. No. 6,465,768 issued to Ker et al. In an integrated circuit, however, passive device requires more chip area to be formed therewith and an RC circuit will increase the loading on the pad it is connected thereto.
In addition, even though conventional ESD protection circuits can enhance the ESD protection device to be easier triggered by pumping the substrate potential, they cannot be provided for the cases of the pads that will be applied with voltages thereon higher than the supply voltage VCC. Readers are referred to the PNP driven NMOS ESD protection circuit disclosed by U.S. Pat. No. 5,982,217 issued to Chen et al. and the substrate pumped ESD network with trench structure disclosed by U.S. Pat. No. 6,411,480 issued to Gauthier et al. for more details.
Therefore, it is desired an ESD protection structure and method with a high driving capability of pumping the substrate potential.